This is a 1024Mx64 bits 8GB(8192MB) DDR3-1600(CL11)-11-11-28 SDRAM memory module, The SPD is programmed to JEDEC standard latency 1600Mbps timing of 11-11-11-28 at 1.5V. The module is composed of six-teen 512Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass–epoxy printed circuit board. The module is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features:\n- Power supply (Normal): VDD & VDDQ = 1.5V ± 0.075V\n- 1.5V (SSTL_15 compatible) I/O\n- MRS Cycle with address key programs\n- CAS Latency (5,6,7,8,9,10,11)\n- Burst Length (BL):8 and 4 with Burst Chop(BC)\n- Bi-directional, differential data strobe (DQS and /DQS)\n- Differential clock input (CK, /CK) operation\n- DLL aligns DQ and DQS transition with CK transition\n- Double-data-rate architecture; two data transfers per clock cycle\n- 8 independent internal bank\n- Internal (self) calibration: Internal self calibration through ZQ pin (RZQ:240 ohm±1%)\n- Auto refresh and self refresh\n- Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE 95°C\n- 8-bit pre-fetch.\n- On Die Termination using ODT pin.\n- Lead-free and Halogen-free products are RoHS Compliant